| Metadata Table | |
|---|---|
| Manual Type | debug |
| Spec Revision | 0.13.2 |
| Spec Release Date | 2019-03-25 |
| Git Revision | task_group_vote-4-g4e0bb0f |
| Git URL | https://github.com/riscv/riscv-debug-spec.git |
| Source | serial.tex |
| Conversion Date | 2023/11/12 |
| License | CC-by-4.0 |
| Address | Name | Page |
|---|---|---|
| 0x34 | Serial Control and Status (sercs) |
|
| 0x35 | Serial TX Data (sertx) |
|
| 0x36 | Serial RX Data (serrx) |
sercs, at 0x34)[sercs]
If serialcountis 0, this register is not present.
| Field | Description | Access | Reset |
|---|---|---|---|
| [serialcount] |serialcount| | Number of supported serial ports. | R | Preset |
| [serial] |serial| | Select which serial port is accessed by serrxand sertx. |
R/W | 0 |
| [error0] |error0| | 1 when the debugger-to-core queue for serial port 0 has over or underflowed. This bit will remain set until it is reset by writing 1 to this bit. | R/W1C | 0 |
| [valid0] |valid0| | 1 when the core-to-debugger queue for serial port 0 is not empty. | R | 0 |
| [full0] |full0| | 1 when the debugger-to-core queue for serial port 0 is full. | R | 0 |
sertx, at 0x35)[sertx]
If serialcountis 0, this register is not present.
This register provides access to the write data queue of the serial port
selected by serialin sercs.
If the error bit is not set and the queue is not full, a write to this register
adds the written data to the core-to-debugger queue.
Otherwise the error bit is set and the write returns error.
A read to this register returns the last data written.
serrx, at 0x36)[serrx]
If serialcountis 0, this register is not present.
This register provides access to the read data queues of the serial port
selected by serialin sercs.
If the error bit is not set and the queue is not empty, a read from this register reads the
oldest entry in the debugger-to-core queue, and removes that entry from the queue.
Otherwise the error bit is set and the read returns error.
This entire register is read-only.
