• 1Introduction
    • 1.1RISC-V Privileged Software Stack Terminology
    • 1.2Privilege Levels
    • 1.3Debug Mode
  • 2Control and Status Registers (CSRs)
    • 2.1CSR Address Mapping Conventions
    • 2.2CSR Listing
    • 2.3CSR Field Specifications
    • 2.4CSR Field Modulation
    • 2.5Implicit Reads of CSRs
    • 2.6CSR Width Modulation
  • 3Machine-Level ISA, Version 1.12
    • 3.1Machine-Level CSRs
      • 3.1.1Machine ISA Register misa
      • 3.1.2Machine Vendor ID Register mvendorid
      • 3.1.3Machine Architecture ID Register marchid
      • 3.1.4Machine Implementation ID Register mimpid
      • 3.1.5Hart ID Register mhartid
      • 3.1.6Machine Status Registers (mstatus and mstatush)
      • 3.1.7Machine Trap-Vector Base-Address Register (mtvec)
      • 3.1.8Machine Trap Delegation Registers (medeleg and mideleg)
      • 3.1.9Machine Interrupt Registers (mip and mie)
      • 3.1.10Hardware Performance Monitor
      • 3.1.11Machine Counter-Enable Register (mcounteren)
      • 3.1.12Machine Counter-Inhibit CSR (mcountinhibit)
      • 3.1.13Machine Scratch Register (mscratch)
      • 3.1.14Machine Exception Program Counter (mepc)
      • 3.1.15Machine Cause Register (mcause)
      • 3.1.16Machine Trap Value Register (mtval)
      • 3.1.17Machine Configuration Pointer Register (mconfigptr)
      • 3.1.19Machine Security Configuration Register (mseccfg)
    • 3.2Machine-Level Memory-Mapped Registers
      • 3.2.1Machine Timer Registers (mtime and mtimecmp)
    • 3.3Machine-Mode Privileged Instructions
      • 3.3.1Environment Call and Breakpoint
      • 3.3.2Trap-Return Instructions
      • 3.3.3Wait for Interrupt
      • 3.3.4Custom SYSTEM Instructions
    • 3.4Reset
    • 3.5Non-Maskable Interrupts
    • 3.6Physical Memory Attributes
      • 3.6.1Main Memory versus I/O versus Vacant Regions
      • 3.6.2Supported Access Type PMAs
      • 3.6.3Atomicity PMAs
      • 3.6.4Memory-Ordering PMAs
      • 3.6.5Coherence and Cacheability PMAs
      • 3.6.6Idempotency PMAs
    • 3.7Physical Memory Protection
      • 3.7.1Physical Memory Protection CSRs
      • 3.7.2Physical Memory Protection and Paging
  • 4Supervisor-Level ISA, Version 1.12
    • 4.1Supervisor CSRs
      • 4.1.1Supervisor Status Register (sstatus)
      • 4.1.2Supervisor Trap Vector Base Address Register (stvec)
      • 4.1.3Supervisor Interrupt Registers (sip and sie)
      • 4.1.4Supervisor Timers and Performance Counters
      • 4.1.5Counter-Enable Register (scounteren)
      • 4.1.6Supervisor Scratch Register (sscratch)
      • 4.1.7Supervisor Exception Program Counter (sepc)
      • 4.1.8Supervisor Cause Register (scause)
      • 4.1.9Supervisor Trap Value (stval) Register
      • 4.1.10Supervisor Environment Configuration Register (senvcfg)
      • 4.1.11Supervisor Address Translation and Protection (satp) Register
    • 4.2Supervisor Instructions
      • 4.2.1Supervisor Memory-Management Fence Instruction
    • 4.3Sv32: Page-Based 32-bit Virtual-Memory Systems
      • 4.3.1Addressing and Memory Protection
      • 4.3.2Virtual Address Translation Process
    • 4.4Sv39: Page-Based 39-bit Virtual-Memory System
      • 4.4.1Addressing and Memory Protection
    • 4.5Sv48: Page-Based 48-bit Virtual-Memory System
      • 4.5.1Addressing and Memory Protection
    • 4.6Sv57: Page-Based 57-bit Virtual-Memory System
      • 4.6.1Addressing and Memory Protection
  • 5Svnapot Standard Extension for NAPOT Translation Contiguity, Version 1.0
  • 6Svpbmt Standard Extension for Page-Based Memory Types, Version 1.0
  • 7Svinval Standard Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0
  • 5Hypervisor Extension, Version 1.0
    • 5.1Privilege Modes
    • 5.2Hypervisor and Virtual Supervisor CSRs
      • 5.2.1Hypervisor Status Register (hstatus)
      • 5.2.2Hypervisor Trap Delegation Registers (hedeleg and hideleg)
      • 5.2.3Hypervisor Interrupt Registers (hvip, hip, and hie)
      • 5.2.4Hypervisor Guest External Interrupt Registers (hgeip and hgeie)
      • 5.2.6Hypervisor Counter-Enable Register (hcounteren)
      • 5.2.7Hypervisor Time Delta Registers (htimedelta, htimedeltah)
      • 5.2.8Hypervisor Trap Value Register (htval)
      • 5.2.9Hypervisor Trap Instruction Register (htinst)
      • 5.2.10Hypervisor Guest Address Translation and Protection Register (hgatp)
      • 5.2.11Virtual Supervisor Status Register (vsstatus)
      • 5.2.12Virtual Supervisor Interrupt Registers (vsip and vsie)
      • 5.2.13Virtual Supervisor Trap Vector Base Address Register (vstvec)
      • 5.2.14Virtual Supervisor Scratch Register (vsscratch)
      • 5.2.15Virtual Supervisor Exception Program Counter (vsepc)
      • 5.2.16Virtual Supervisor Cause Register (vscause)
      • 5.2.17Virtual Supervisor Trap Value Register (vstval)
      • 5.2.18Virtual Supervisor Address Translation and Protection Register (vsatp)
    • 5.3Hypervisor Instructions
      • 5.3.1Hypervisor Virtual-Machine Load and Store Instructions
      • 5.3.2Hypervisor Memory-Management Fence Instructions
    • 5.4Machine-Level CSRs
      • 5.4.1Machine Status Registers (mstatus and mstatush)
      • 5.4.2Machine Interrupt Delegation Register (mideleg)
      • 5.4.3Machine Interrupt Registers (mip and mie)
      • 5.4.4Machine Second Trap Value Register (mtval2)
      • 5.4.5Machine Trap Instruction Register (mtinst)
    • 5.5Two-Stage Address Translation
      • 5.5.1Guest Physical Address Translation
      • 5.5.2Guest-Page Faults
      • 5.5.3Memory-Management Fences
    • 5.6Traps
      • 5.6.1Trap Cause Codes
      • 5.6.2Trap Entry
      • 5.6.3Transformed Instruction or Pseudoinstruction for mtinst or htinst
      • 5.6.4Trap Return
  • 6Machine Configuration Description
    • 6.1Configuration String Search Procedure
  • 7Platform-Level Interrupt Controller (PLIC)
    • 7.1PLIC Overview
    • 7.2Interrupt Sources
      • 7.2.1Local Interrupt Sources
      • 7.2.2Global Interrupt Sources
    • 7.3Interrupt Targets and Hart Contexts
    • 7.4Interrupt Gateways
    • 7.5Interrupt Identifiers (IDs)
    • 7.6Interrupt Priorities
    • 7.7Interrupt Enables
    • 7.8Interrupt Priority Thresholds
    • 7.9Interrupt Notifications
    • 7.10Interrupt Claims
    • 7.11Interrupt Completion
    • 7.12Interrupt Flow
    • 7.13PLIC Core Specification
    • 7.14Controlling Access to the PLIC
  • 8RISC-V Privileged Instruction Set Listings
  • 9History
    • 9.1Research Funding at UC Berkeley