• 1Introduction
  • 1.1RISC-V Privileged Software Stack Terminology
  • 1.2Privilege Levels
  • 1.3Debug Mode
• 1Control and Status Registers (CSRs)
  • 1.1CSR Address Mapping Conventions
  • 1.2CSR Listing
  • 1.3CSR Field Specifications
  • 1.4CSR Field Modulation
  • 1.5Implicit Reads of CSRs
  • 1.6CSR Width Modulation
  • 1.7Explicit Accesses to CSRs Wider than XLEN
• 1Machine-Level ISA, Version 1.12
  • 1.1Machine-Level CSRs
  • 1.2Machine-Level Memory-Mapped Registers
  • 1.3Machine-Mode Privileged Instructions
  • 1.4Reset
  • 1.5Non-Maskable Interrupts
  • 1.6Physical Memory Attributes
  • 1.7Physical Memory Protection
  • 1.1RNMI Interrupt Signals
  • 1.2RNMI Handler Addresses
  • 1.3RNMI CSRs
  • 1.4MNRET Instruction
  • 1.5RNMI Operation
• 1Supervisor-Level ISA, Version 1.12
  • 1.1Supervisor CSRs
  • 1.2Supervisor Instructions
  • 1.3Sv32: Page-Based 32-bit Virtual-Memory Systems
  • 1.4Sv39: Page-Based 39-bit Virtual-Memory System
  • 1.5Sv48: Page-Based 48-bit Virtual-Memory System
  • 1.6Sv57: Page-Based 57-bit Virtual-Memory System
• 1Hypervisor Extension, Version 1.0
  • 1.1Privilege Modes
  • 1.2Hypervisor and Virtual Supervisor CSRs
  • 1.3Hypervisor Instructions
  • 1.4Machine-Level CSRs
  • 1.5Two-Stage Address Translation
  • 1.6Traps
• 1RISC-V Privileged Instruction Set Listings
• 1History
  • 1.1Research Funding at UC Berkeley
• Bibliography