• 1Introduction
  • 1.1RISC-V Hardware Platform Terminology
  • 1.2RISC-V Privileged Software Stack Terminology
  • 1.3Privilege Levels
  • 1.4Debug Mode
• 2Control and Status Registers (CSRs)
  • 2.1CSR Address Mapping Conventions
  • 2.2CSR Listing
  • 2.3CSR Field Specifications
• 3Machine-Level ISA, version 1.10
  • 3.1Machine-Level CSRs
    • 3.1.1Machine ISA Register misa
    • 3.1.2Machine Vendor ID Register mvendorid
    • 3.1.3Machine Architecture ID Register marchid
    • 3.1.4Machine Implementation ID Register mimpid
    • 3.1.5Hart ID Register mhartid
    • 3.1.6Machine Status Register (mstatus)
    • 3.1.7Privilege and Global Interrupt-Enable Stack in mstatus register
    • 3.1.8Base ISA Control in mstatus Register
    • 3.1.9Memory Privilege in mstatus Register
    • 3.1.10Virtualization Support in mstatus Register
    • 3.1.11Extension Context Status in mstatus Register
    • 3.1.12Machine Trap-Vector Base-Address Register (mtvec)
    • 3.1.13Machine Trap Delegation Registers (medeleg and mideleg)
    • 3.1.14Machine Interrupt Registers (mip and mie)
    • 3.1.15Machine Timer Registers (mtime and mtimecmp)
    • 3.1.16Hardware Performance Monitor
    • 3.1.17Counter-Enable Registers ([m|h|s]counteren)
    • 3.1.18Machine Scratch Register (mscratch)
    • 3.1.19Machine Exception Program Counter (mepc)
    • 3.1.20Machine Cause Register (mcause)
    • 3.1.21Machine Trap Value (mtval) Register
  • 3.2Machine-Mode Privileged Instructions
    • 3.2.1Environment Call and Breakpoint
    • 3.2.2Trap-Return Instructions
    • 3.2.3Wait for Interrupt
  • 3.3Reset
  • 3.4Non-Maskable Interrupts
  • 3.5Physical Memory Attributes
    • 3.5.1Main Memory versus I/O versus Empty Regions
    • 3.5.2Supported Access Type PMAs
    • 3.5.3Atomicity PMAs
    • 3.5.4Memory-Ordering PMAs
    • 3.5.5Coherence and Cacheability PMAs
    • 3.5.6Idempotency PMAs
  • 3.6Physical Memory Protection
    • 3.6.1Physical Memory Protection CSRs
• 4Supervisor-Level ISA, Version 1.10
  • 4.1Supervisor CSRs
    • 4.1.1Supervisor Status Register (sstatus)
    • 4.1.2Base ISA Control in sstatus Register
    • 4.1.3Memory Privilege in sstatus Register
    • 4.1.4Supervisor Trap Vector Base Address Register (stvec)
    • 4.1.5Supervisor Interrupt Registers (sip and sie)
    • 4.1.6Supervisor Timers and Performance Counters
    • 4.1.7Counter-Enable Register (scounteren)
    • 4.1.8Supervisor Scratch Register (sscratch)
    • 4.1.9Supervisor Exception Program Counter (sepc)
    • 4.1.10Supervisor Cause Register (scause)
    • 4.1.11Supervisor Trap Value (stval) Register
    • 4.1.12Supervisor Address Translation and Protection (satp) Register
  • 4.2Supervisor Instructions
    • 4.2.1Supervisor Memory-Management Fence Instruction
  • 4.3Sv32: Page-Based 32-bit Virtual-Memory Systems
    • 4.3.1Addressing and Memory Protection
    • 4.3.2Virtual Address Translation Process
  • 4.4Sv39: Page-Based 39-bit Virtual-Memory System
    • 4.4.1Addressing and Memory Protection
  • 4.5Sv48: Page-Based 48-bit Virtual-Memory System
    • 4.5.1Addressing and Memory Protection
• 5Hypervisor Extensions, Version 0.0
• 6Machine Configuration Description
  • 6.1Configuration String Search Procedure
• 7Platform-Level Interrupt Controller (PLIC)
  • 7.1PLIC Overview
  • 7.2Interrupt Sources
    • 7.2.1Local Interrupt Sources
    • 7.2.2Global Interrupt Sources
  • 7.3Interrupt Targets and Hart Contexts
  • 7.4Interrupt Gateways
  • 7.5Interrupt Identifiers (IDs)
  • 7.6Interrupt Priorities
  • 7.7Interrupt Enables
  • 7.8Interrupt Priority Thresholds
  • 7.9Interrupt Notifications
  • 7.10Interrupt Claims
  • 7.11Interrupt Completion
  • 7.12Interrupt Flow
  • 7.13PLIC Core Specification
  • 7.14Controlling Access to the PLIC
• 8RISC-V Privileged Instruction Set Listings
• 9History
  • 9.1Research Funding at UC Berkeley