• Preface
• 1Introduction
  • 1.1RISC-V Hardware Platform Terminology
  • 1.2RISC-V Software Execution Environments and Harts
  • 1.3RISC-V ISA Overview
  • 1.4Instruction Length Encoding
  • 1.5Exceptions, Traps, and Interrupts
• 2RV32I Base Integer Instruction Set, Version 2.1
  • 2.1Programmers Model for Base Integer ISA
  • 2.2Base Instruction Formats
  • 2.3Immediate Encoding Variants
  • 2.4Integer Computational Instructions
  • 2.5Control Transfer Instructions
  • 2.6Load and Store Instructions
  • 2.7Memory Ordering Instructions
  • 2.8Environment Call and Breakpoints
  • 2.9HINT Instructions
• 3Zifencei Instruction-Fetch Fence, Version 2.0
• 5RV32E Base Integer Instruction Set, Version 1.9
  • 5.1RV32E Programmers Model
  • 5.2RV32E Instruction Set
• 6RV64I Base Integer Instruction Set, Version 2.1
  • 6.1Register State
  • 6.2Integer Computational Instructions
  • 6.3Load and Store Instructions
  • 6.4HINT Instructions
• 7RV128I Base Integer Instruction Set, Version 1.7
• 8M Standard Extension for Integer Multiplication and
  • 8.1Multiplication Operations
  • 8.2Division Operations
• 9A Standard Extension for Atomic Instructions, Version 2.0
  • 9.1Specifying Ordering of Atomic Instructions
  • 9.2Load-Reserved/Store-Conditional Instructions
  • 9.3Atomic Memory Operations
• 10Zicsr, Control and Status Register (CSR) Instructions, Version 2.0
  • 10.1CSR Instructions
• 11Counters
  • 11.1Base Counters and Timers
  • 11.2Hardware Performance Counters
• 12F Standard Extension for Single-Precision Floating-Point,
  • 12.1F Register State
  • 12.2Floating-Point Control and Status Register
  • 12.3NaN Generation and Propagation
  • 12.4Subnormal Arithmetic
  • 12.5Single-Precision Load and Store Instructions
  • 12.6Single-Precision Floating-Point Computational Instructions
  • 12.7Single-Precision Floating-Point Conversion and Move Instructions
  • 12.8Single-Precision Floating-Point Compare Instructions
  • 12.9Single-Precision Floating-Point Classify Instruction
• 13D Standard Extension for Double-Precision Floating-Point,
  • 13.1D Register State
  • 13.2NaN Boxing of Narrower Values
  • 13.3Double-Precision Load and Store Instructions
  • 13.4Double-Precision Floating-Point Computational Instructions
  • 13.5Double-Precision Floating-Point Conversion and Move Instructions
  • 13.6Double-Precision Floating-Point Compare Instructions
  • 13.7Double-Precision Floating-Point Classify Instruction
• 14Q Standard Extension for Quad-Precision Floating-Point,
  • 14.1Quad-Precision Load and Store Instructions
  • 14.2Quad-Precision Computational Instructions
  • 14.3Quad-Precision Convert and Move Instructions
  • 14.4Quad-Precision Floating-Point Compare Instructions
  • 14.5Quad-Precision Floating-Point Classify Instruction
• 16RVWMO Memory Consistency Model, Version 0.1
  • 16.1Definition of the RVWMO Memory Model
• 17C Standard Extension for Compressed Instructions, Version
  • 17.1Overview
  • 17.2Compressed Instruction Formats
  • 17.3Load and Store Instructions
  • 17.4Control Transfer Instructions
  • 17.5Integer Computational Instructions
  • 17.6Usage of C Instructions in LR/SC Sequences
  • 17.7HINT Instructions
  • 17.8RVC Instruction Set Listings
• 18B Standard Extension for Bit Manipulation, Version 0.0
• 19J Standard Extension for Dynamically Translated Languages, Version 0.0
• 20P Standard Extension for Packed-SIMD Instructions,
• 21V Standard Extension for Vector Operations, Version 0.4-DRAFT
  • 21.1Vector Unit State
  • 21.2Vector Unit Type Configuration Register (vtypen)
  • 21.3Shape Encoding
  • 21.4Representation Encoding
  • 21.5Element Bitwidth
  • 21.6Base Vector Extension Supported Types
  • 21.7Maximum Vector Element Width (vmaxew)
  • 21.8Vector Configuration Registers (vcfg0vcfg15)
  • 21.9Legal Vector Unit Configurations
  • 21.10Vector Unit CSRs
  • 21.11Maximum Vector Length (MVL)
  • 21.12Vector Instruction Formats
  • 21.13Polymorphic Vector Instructions
  • 21.14Rapid Configuration Instructions
  • 21.15Vector-Type-Change Instructions
  • 21.16Vector Length
  • 21.17Predicated Execution
  • 21.18Vector Load/Store Instructions
  • 21.19Vector Register Gather
  • 21.20Vector Slide
  • 21.21Fixed-Point Support
  • 21.22Optional Transcendental Support
  • 21.23Instruction-Set Encoding
• 22Zam Standard Extension for Misaligned Atomics, v0.1
• 24Ztso Standard Extension for Total Store Ordering, v0.1
• 25RV32/64G Instruction Set Listings
• 26Extending RISC-V
  • 26.1Extension Terminology
  • 26.2RISC-V Extension Design Philosophy
  • 26.3Extensions within fixed-width 32-bit instruction format
  • 26.4Adding aligned 64-bit instruction extensions
  • 26.5Supporting VLIW encodings
• 27ISA Subset Naming Conventions
  • 27.1Case Sensitivity
  • 27.2Base Integer ISA
  • 27.3Instruction Extensions Names
  • 27.4Version Numbers
  • 27.5Underscores
  • 27.6Non-Standard Extension Names
  • 27.7Supervisor-level Instruction Subsets
  • 27.8Supervisor-level Extensions
  • 27.9Subset Naming Convention
• 28History and Acknowledgments
  • 28.1Why Develop a new ISA? Rationale from Berkeley Group
  • 28.2History from Revision 1.0 of ISA manual
  • 28.3History from Revision 2.0 of ISA manual
  • 28.4History from Revision 2.1
  • 28.5History from Revision 2.2
  • 28.6History for Revision 2.3
  • 28.7Funding
• CSR Dependency Tracking Granularity
• Source and Destination Register Listings
• RVWMO Explanatory Material, Version 0.1
  • Why RVWMO?
  • Litmus Tests
  • Explaining the RVWMO Rules
    • Preserved Program Order and Global Memory Order
    • Overlapping-Address Orderings (Rules[ppo:->st][ppo:amoforward])
    • Fences (Rule[ppo:fence])
    • Explicit Synchronization (Rules[ppo:acquire][ppo:pair])
    • Syntactic Dependencies (Rules[ppo:addr][ppo:ctrl])
    • Pipeline Dependencies (Rules[ppo:addrdatarfi][ppo:addrpo])
  • Beyond Main Memory
    • Coherence and Cacheability
    • I/O Ordering
  • Code Porting and Mapping Guidelines
  • Implementation Guidelines
    • Possible Future Extensions
  • Known Issues
    • Mixed-size RSW
• Formal Memory Model Specifications, Version 0.1
• Formal Axiomatic Specification in Alloy
• Formal Axiomatic Specification in Herd
• An Operational Memory Model
  • Intra-instruction Pseudocode Execution
  • Instruction Instance State
  • Hart State
  • Shared Memory State
  • Transitions
  • Limitations