| Metadata Table | |
|---|---|
| Manual Type | user |
| Spec Revision | 20181106-Base-Ratification |
| Spec Release Date | |
| Git Revision | 20181106-Base-Ratification |
| Git URL | https://github.com/riscv/riscv-isa-manual.git |
| Source | src/memory-model-alloy.tex |
| Conversion Date | 2023/11/12 |
| License | CC-by-4.0 |
We present a formal specification of the RVWMO memory model in Alloy (http://alloy.mit.edu). This model is available online at https://github.com/daniellustig/riscv-memory-model.
The online material also contains some litmus tests and some examples of how Alloy can be used to model check some of the mappings in Section [sec:memory:porting].