Preface

This document describes the RISC-V unprivileged architecture. This release 20181106-Base-Ratification will be used in ratifying the base and standard extensions described below.

The RISC-V RVWMO memory model has been ratified at this time. The ISA modules marked Ratification are scheduled for ratification with this release of the specification. The modules marked Frozen are not expected to change before being put up for ratification. The modules marked Draft are expected to change before ratification.

The document contains the following versions of the RISC-V ISA modules:

The changes in this version of the document include:

• Changed document version scheme to avoid confusion with versions of the ISA modules.

• Incremented the version numbers of the base integer ISA to 2.1, reflecting the presence of the ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA.

• Incremented the version numbers of the F and D extensions to 2.2, reflecting that version 2.1 changed the canonical NaN, and version 2.2 defined the NaN-boxing scheme and changed the definition of the FMIN and FMAX instructions.

• Changed name of document to refer to “unprivileged” instructions as part of move to separate ISA specifications from platform profile mandates.

• Added clearer and more precise definitions of execution environments, harts, and traps.

• Defined instruction-set categories: standard, reserved, custom, non-standard, and non-conforming.

• Removed text implying operation under alternate endianness, as alternate-endianness operation has not yet been defined for RISC-V.

• Changed description of misaligned load and store behavior. The specification now allows visible misaligned address traps in execution environment interfaces, rather than just mandating invisible handling of misaligned loads and stores in user mode. Also, now allows access exceptions to be reported for misaligned accesses (including atomics) that should not be emulated.

• Moved FENCE.I out of the mandatory base and into a separate extension, with Zifencei ISA name. FENCE.I was removed from the Linux user ABI and is problematic in implementations with large incoherent instruction and data caches. However, it remains the only standard instruction-fetch coherence mechanism.

• Removed prohibitions on using RV32E with other extensions.

• Removed platform-specific mandates that certain encodings produce illegal instruction exceptions in RV32E and RV64I chapters.

• Counter/timer instructions are now not considered part of the mandatory base ISA, and so CSR instructions were moved into separate chapter and marked as version 2.0, with the unprivileged counters moved into another separate chapter. The counters are not ready for ratification as there are outstanding issues, including counter inaccuracies, and effect of RDTIME with respect to the memory model ordering constraints.

• Explicitly defined the 16-bit half-precision floating-point format for floating-point instructions in the 2-bit fmt field.

• Defined the signed-zero behavior of FMIN.fmt and FMAX.fmt, and changed their behavior on signaling-NaN inputs to conform to the minimumNumber and maximumNumber operations in the proposed IEEE 754-201x specification.

• The memory consistency model, RVWMO, has been defined.

• The “Zam” extension, which permits misaligned AMOs and specifies their semantics, has been defined.

• The “Ztso” extension, which enforces a stricter memory consistency model than RVWMO, has been defined.

• Improvements to the description and commentary.

• Defined the term IALIGN as shorthand to describe the instruction-address alignment constraint.

Preface to Document Version 2.2

This is version 2.2 of the document describing the RISC-V user-level architecture. The document contains the following versions of the RISC-V ISA modules:

To date, no parts of the standard have been officially ratified by the RISC-V Foundation, but the components labeled “frozen” above are not expected to change during the ratification process beyond resolving ambiguities and holes in the specification.

The major changes in this version of the document include:

• The previous version of this document was released under a Creative Commons Attribution 4.0 International License by the original authors, and this and future versions of this document will be released under the same license.

• Rearranged chapters to put all extensions first in canonical order.

• Improvements to the description and commentary.

• Modified implicit hinting suggestion on JALR to support more efficient macro-op fusion of LUI/JALR and AUIPC/JALR pairs.

• Clarification of constraints on load-reserved/store-conditional sequences.

• A new table of control and status register (CSR) mappings.

• Clarified purpose and behavior of high-order bits of fcsr.

• Corrected the description of the FNMADD.fmt and FNMSUB.fmt instructions, which had suggested the incorrect sign of a zero result.

• Instructions FMV.S.X and FMV.X.S were renamed to FMV.W.X and FMV.X.W respectively to be more consistent with their semantics, which did not change. The old names will continue to be supported in the tools.

• Specified behavior of narrower (<FLEN) floating-point values held in wider f registers using NaN-boxing model.

• Defined the exception behavior of FMA(∞, 0, qNaN).

• Added note indicating that the P extension might be reworked into an integer packed-SIMD proposal for fixed-point operations using the integer registers.

• A draft proposal of the V vector instruction-set extension.

• An early draft proposal of the N user-level traps extension.

• An expanded pseudoinstruction listing.

• Removal of the calling convention chapter, which has been superseded by the RISC-V ELF psABI Specification [riscv-elf-psabi].

• The C extension has been frozen and renumbered version 2.0.

Preface to Document Version 2.1

This is version 2.1 of the document describing the RISC-V user-level architecture. Note the frozen user-level ISA base and extensions IMAFDQ version 2.0 have not changed from the previous version of this document [riscvtr2], but some specification holes have been fixed and the documentation has been improved. Some changes have been made to the software conventions.

• Numerous additions and improvements to the commentary sections.

• Separate version numbers for each chapter.

• Modification to long instruction encodings >64 bits to avoid moving the rd specifier in very long instruction formats.

• CSR instructions are now described in the base integer format where the counter registers are introduced, as opposed to only being introduced later in the floating-point section (and the companion privileged architecture manual).

• The SCALL and SBREAK instructions have been renamed to ECALL and EBREAK, respectively. Their encoding and functionality are unchanged.

• Clarification of floating-point NaN handling, and a new canonical NaN value.

• Clarification of values returned by floating-point to integer conversions that overflow.

• Clarification of LR/SC allowed successes and required failures, including use of compressed instructions in the sequence.

• A new RV32E base ISA proposal for reduced integer register counts, supports MAC extensions.

• A revised calling convention.

• Relaxed stack alignment for soft-float calling convention, and description of the RV32E calling convention.

• A revised proposal for the C compressed extension, version 1.9.

Preface to Version 2.0

This is the second release of the user ISA specification, and we intend the specification of the base user ISA plus general extensions (i.e., IMAFD) to remain fixed for future development. The following changes have been made since Version 1.0 [riscvtr] of this ISA specification.

• The ISA has been divided into an integer base with several standard extensions.

• The instruction formats have been rearranged to make immediate encoding more efficient.

• The base ISA has been defined to have a little-endian memory system, with big-endian or bi-endian as non-standard variants.

• Load-Reserved/Store-Conditional (LR/SC) instructions have been added in the atomic instruction extension.

• AMOs and LR/SC can support the release consistency model.

• The FENCE instruction provides finer-grain memory and I/O orderings.

• An AMO for fetch-and-XOR (AMOXOR) has been added, and the encoding for AMOSWAP has been changed to make room.

• The AUIPC instruction, which adds a 20-bit upper immediate to the PC, replaces the RDNPC instruction, which only read the current PC value. This results in significant savings for position-independent code.

• The JAL instruction has now moved to the U-Type format with an explicit destination register, and the J instruction has been dropped being replaced by JAL with rd=x0. This removes the only instruction with an implicit destination register and removes the J-Type instruction format from the base ISA. There is an accompanying reduction in JAL reach, but a significant reduction in base ISA complexity.

• The static hints on the JALR instruction have been dropped. The hints are redundant with the rd and rs1 register specifiers for code compliant with the standard calling convention.

• The JALR instruction now clears the lowest bit of the calculated target address, to simplify hardware and to allow auxiliary information to be stored in function pointers.

• The MFTX.S and MFTX.D instructions have been renamed to FMV.X.S and FMV.X.D, respectively. Similarly, MXTF.S and MXTF.D instructions have been renamed to FMV.S.X and FMV.D.X, respectively.

• The MFFSR and MTFSR instructions have been renamed to FRCSR and FSCSR, respectively. FRRM, FSRM, FRFLAGS, and FSFLAGS instructions have been added to individually access the rounding mode and exception flags subfields of the fcsr.

• The FMV.X.S and FMV.X.D instructions now source their operands from rs1, instead of rs2. This change simplifies datapath design.

• FCLASS.S and FCLASS.D floating-point classify instructions have been added.

• A simpler NaN generation and propagation scheme has been adopted.

• For RV32I, the system performance counters have been extended to 64-bits wide, with separate read access to the upper and lower 32 bits.

• Canonical NOP and MV encodings have been defined.

• Standard instruction-length encodings have been defined for 48-bit, 64-bit, and >64-bit instructions.

• Description of a 128-bit address space variant, RV128, has been added.

• Major opcodes in the 32-bit base instruction format have been allocated for user-defined custom extensions.

• A typographical error that suggested that stores source their data from rd has been corrected to refer to rs2.