Metadata Table | |
---|---|
Manual Type | user |
Spec Revision | 20191214- |
Spec Release Date | December 2019 |
Git Revision | Priv-v1.12 |
Git URL | https://github.com/riscv/riscv-isa-manual.git |
Source | src/dep-table.tex |
Conversion Date | 2023/11/12 |
License | CC-by-4.0 |
Name | Portions Tracked as Independent Units | Aliases |
---|---|---|
fflags |
Bits 4, 3, 2, 1, 0 | fcsr |
frm |
entire CSR | fcsr |
fcsr |
Bits 7-5, 4, 3, 2, 1, 0 | fflags , frm |
Note: read-only CSRs are not listed, as they do not participate in the definition of syntactic dependencies.
This section provides a concrete listing of the source and destination registers for each instruction. These listings are used in the definition of syntactic dependencies in Section [sec:memorymodel:dependencies].
The term “accumulating CSR” is used to describe a CSR that is both a source and a destination register, but which carries a dependency only from itself to itself.
Instructions carry a dependency from each source register in the “Source Registers” column to each destination register in the “Destination Registers” column, from each source register in the “Source Registers” column to each CSR in the “Accumulating CSRs” column, and from each CSR in the “Accumulating CSRs” column to itself, except where annotated otherwise.
Key:
AAddress source register
DData source register
†The instruction does not carry a dependency from any source register to any destination register
‡The instruction carries dependencies from source register(s) to destination register(s) as specified