• 1Introduction
  • 1.1RISC-V Hardware Platform Terminology
  • 1.2RISC-V Software Execution Environments and Harts
  • 1.3RISC-V ISA Overview
  • 1.4Memory
  • 1.5Base Instruction-Length Encoding
  • 1.6Exceptions, Traps, and Interrupts
  • 1.7UNSPECIFIED Behaviors and Values
• 1RV32I Base Integer Instruction Set, Version 2.1
  • 1.1Programmers Model for Base Integer ISA
  • 1.2Base Instruction Formats
  • 1.3Immediate Encoding Variants
  • 1.4Integer Computational Instructions
  • 1.5Control Transfer Instructions
  • 1.6Load and Store Instructions
  • 1.7Memory Ordering Instructions
  • 1.8Environment Call and Breakpoints
  • 1.9HINT Instructions
• 1RV32E and RV64E Base Integer Instruction Sets, Version 2.0
  • 1.1RV32E and RV64E Programmers Model
  • 1.2RV32E and RV64E Instruction Set Encoding
• 1RV64I Base Integer Instruction Set, Version 2.1
  • 1.1Register State
  • 1.2Integer Computational Instructions
  • 1.3Load and Store Instructions
  • 1.4HINT Instructions
• 1RV128I Base Integer Instruction Set, Version 1.7
  • 1.1Multiplication Operations
  • 1.2Division Operations
  • 1.3Zmmul Extension, Version 1.0
  • 1.1Specifying Ordering of Atomic Instructions
  • 1.2Load-Reserved/Store-Conditional Instructions
  • 1.3Eventual Success of Store-Conditional Instructions
  • 1.4Atomic Memory Operations
  • 1.1CSR Instructions
  • 1.1F Register State
  • 1.2Floating-Point Control and Status Register
  • 1.3NaN Generation and Propagation
  • 1.4Subnormal Arithmetic
  • 1.5Single-Precision Load and Store Instructions
  • 1.6Single-Precision Floating-Point Computational Instructions
  • 1.7Single-Precision Floating-Point Conversion and Move Instructions
  • 1.8Single-Precision Floating-Point Compare Instructions
  • 1.9Single-Precision Floating-Point Classify Instruction
  • 1.1D Register State
  • 1.2NaN Boxing of Narrower Values
  • 1.3Double-Precision Load and Store Instructions
  • 1.4Double-Precision Floating-Point Computational Instructions
  • 1.5Double-Precision Floating-Point Conversion and Move Instructions
  • 1.6Double-Precision Floating-Point Compare Instructions
  • 1.7Double-Precision Floating-Point Classify Instruction
  • 1.1Quad-Precision Load and Store Instructions
  • 1.2Quad-Precision Computational Instructions
  • 1.3Quad-Precision Convert and Move Instructions
  • 1.4Quad-Precision Floating-Point Compare Instructions
  • 1.5Quad-Precision Floating-Point Classify Instruction
  • 1.1Half-Precision Load and Store Instructions
  • 1.2Half-Precision Computational Instructions
  • 1.3Half-Precision Conversion and Move Instructions
  • 1.4Half-Precision Floating-Point Compare Instructions
  • 1.5Half-Precision Floating-Point Classify Instruction
• 1RVWMO Memory Consistency Model, Version 2.0
  • 1.1Definition of the RVWMO Memory Model
  • 1.2CSR Dependency Tracking Granularity
  • 1.3Source and Destination Register Listings
  • 1.1Overview
  • 1.2Compressed Instruction Formats
  • 1.3Load and Store Instructions
  • 1.4Control Transfer Instructions
  • 1.5Integer Computational Instructions
  • 1.6Usage of C Instructions in LR/SC Sequences
  • 1.7HINT Instructions
  • 1.8RVC Instruction Set Listings
  • 1.1Atomicity Axiom for misaligned atomics
  • 1.1Processing of Narrower Values
  • 1.2Zdinx
  • 1.3Processing of Wider Values
  • 1.4Zhinx
  • 1.5Zhinxmin
  • 1.6Privileged Architecture Implications
  • 1.1Load-Immediate Instructions
  • 1.2Minimum and Maximum Instructions
  • 1.3Round-to-Integer Instructions
  • 1.4Modular Convert-to-Integer Instruction
  • 1.5Move Instructions
  • 1.6Comparison Instructions
• 1RV32/64G Instruction Set Listings
• 1Extending RISC-V
  • 1.1Extension Terminology
  • 1.2RISC-V Extension Design Philosophy
  • 1.3Extensions within fixed-width 32-bit instruction format
  • 1.4Adding aligned 64-bit instruction extensions
  • 1.5Supporting VLIW encodings
• 1ISA Extension Naming Conventions
  • 1.1Case Sensitivity
  • 1.2Base Integer ISA
  • 1.3Instruction-Set Extension Names
  • 1.4Version Numbers
  • 1.5Underscores
  • 1.6Additional Standard Extension Names
  • 1.7Supervisor-level Instruction-Set Extensions
  • 1.8Machine-level Instruction-Set Extensions
  • 1.9Non-Standard Extension Names
  • 1.10Subset Naming Convention
• 1History and Acknowledgments
  • 1.2History from Revision 1.0 of ISA manual
  • 1.3History from Revision 2.0 of ISA manual
  • 1.4Acknowledgments
  • 1.5History from Revision 2.1
  • 1.6Acknowledgments
  • 1.7History from Revision 2.2
  • 1.8Acknowledgments
  • 1.9History for Revision 2.3
  • 1.10Funding
• Appendix A: RVWMO Explanatory Material, Version 0.1
  • A.1. Why RVWMO?
  • A.2. Litmus Tests
  • A.3. Explaining the RVWMO Rules
  • A.4. Beyond Main Memory
  • A.5. Code Porting and Mapping Guidelines
  • A.6. Implementation Guidelines
  • A.7. Known Issues
• Appendix A: Formal Memory Model Specifications, Version 0.1
  • A.1. Formal Axiomatic Specification in Alloy
  • A.2. Formal Axiomatic Specification in Herd
  • A.3. An Operational Memory Model
• Index
• Bibliography