• 1Introduction
  • 2Implementation-defined Constant Parameters
  • 3Vector Extension Programmer’s Model
    • 3.1Vector Registers
    • 3.2Vector type register, vtype
    • 3.3Vector Length Register vl
    • 3.4Vector Start Index CSR vstart
    • 3.5Vector Fixed-Point Rounding Mode Register vxrm
    • 3.6Vector Fixed-Point Saturation Flag vxsat
    • 3.7Vector Fixed-Point Fields in fcsr
    • 3.8State of Vector Extension at Reset
  • 4Mapping of Vector Elements to Vector Register State
    • 4.1Mapping with LMUL=1
    • 4.2Mapping with LMUL > 1
    • 4.3Mapping across Mixed-Width Operations
    • 4.4Mask Register Layout
  • 5Vector Instruction Formats
    • 5.1Scalar operands
    • 5.2Vector Operands
    • 5.3Vector Masking
    • 5.4Prestart, Active, Inactive, Body, and Tail Element Definitions
  • 6Configuration-Setting Instructions
    • 6.2Constraints on Setting vl
    • 6.4Examples
  • 7Vector Loads and Stores
    • 7.1Vector Load/Store Instruction Encoding
    • 7.2Vector Load/Store Addressing Modes
    • 7.3Vector Load/Store Width Encoding
    • 7.4Vector Unit-Stride Instructions
    • 7.5Vector Strided Instructions
    • 7.6Vector Indexed Instructions
    • 7.7Unit-stride Fault-Only-First Loads
    • 7.8Vector Load/Store Segment Instructions (Zvlsseg)
  • 8Vector AMO Operations (Zvamo)
  • 9Vector Memory Alignment Constraints
  • 10Vector Memory Consistency Model
  • 11Vector Arithmetic Instruction Formats
    • 11.1Vector Arithmetic Instruction encoding
    • 11.2Widening Vector Arithmetic Instructions
    • 11.3Narrowing Vector Arithmetic Instructions
  • 12Vector Integer Arithmetic Instructions
    • 12.1Vector Single-Width Integer Add and Subtract
    • 12.2Vector Widening Integer Add/Subtract
    • 12.3Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
    • 12.4Vector Bitwise Logical Instructions
    • 12.5Vector Single-Width Bit Shift Instructions
    • 12.6Vector Narrowing Integer Right Shift Instructions
    • 12.7Vector Integer Comparison Instructions
    • 12.8Vector Integer Min/Max Instructions
    • 12.9Vector Single-Width Integer Multiply Instructions
    • 12.10Vector Integer Divide Instructions
    • 12.11Vector Widening Integer Multiply Instructions
    • 12.12Vector Single-Width Integer Multiply-Add Instructions
    • 12.13Vector Widening Integer Multiply-Add Instructions
    • 12.14Vector Integer Merge and Move Instructions
  • 13Vector Fixed-Point Arithmetic Instructions
    • 13.1Vector Single-Width Saturating Add and Subtract
    • 13.2Vector Single-Width Averaging Add and Subtract
    • 13.3Vector Single-Width Fractional Multiply with Rounding and Saturation
    • 13.4Vector Widening Saturating Scaled Multiply-Add
    • 13.5Vector Single-Width Scaling Shift Instructions
    • 13.6Vector Narrowing Fixed-Point Clip Instructions
  • 14Vector Floating-Point Instructions
    • 14.1Vector Floating-Point Exception Flags
    • 14.2Vector Single-Width Floating-Point Add/Subtract Instructions
    • 14.3Vector Widening Floating-Point Add/Subtract Instructions
    • 14.4Vector Single-Width Floating-Point Multiply/Divide Instructions
    • 14.5Vector Widening Floating-Point Multiply
    • 14.6Vector Single-Width Floating-Point Fused Multiply-Add Instructions
    • 14.7Vector Widening Floating-Point Fused Multiply-Add Instructions
    • 14.8Vector Floating-Point Square-Root Instruction
    • 14.9Vector Floating-Point MIN/MAX Instructions
    • 14.10Vector Floating-Point Sign-Injection Instructions
    • 14.11Vector Floating-Point Compare Instructions
    • 14.12Vector Floating-Point Classify Instruction
    • 14.13Vector Floating-Point Merge Instruction
    • 14.14Single-Width Floating-Point/Integer Type-Convert Instructions
    • 14.15Widening Floating-Point/Integer Type-Convert Instructions
    • 14.16Narrowing Floating-Point/Integer Type-Convert Instructions
  • 15Vector Reduction Operations
    • 15.1Vector Single-Width Integer Reduction Instructions
    • 15.2Vector Widening Integer Reduction Instructions
    • 15.3Vector Single-Width Floating-Point Reduction Instructions
    • 15.4Vector Widening Floating-Point Reduction Instructions
  • 16Vector Mask Instructions
    • 16.1Vector Mask-Register Logical Instructions
    • 16.2Vector mask population count vmpopc
    • 16.7Example using vector mask instructions
    • 16.8Vector Iota Instruction
    • 16.9Vector Element Index Instruction
  • 17Vector Permutation Instructions
    • 17.1Integer Extract Instruction
    • 17.2Integer Scalar Move Instruction
    • 17.3Floating-Point Scalar Move Instructions
    • 17.4Vector Slide Instructions
    • 17.5Vector Register Gather Instruction
    • 17.6Vector Compress Instruction
  • 18Exception Handling
    • 18.1Precise vector traps
    • 18.2Imprecise vector traps
    • 18.3Selectable precise/imprecise traps
    • 18.4Swappable traps
  • 19Divided Element Extension (Zvediv)
    • 19.1Instructions not affected by EDIV
    • 19.2Instructions Affected by EDIV
    • 19.3Vector Integer Dot-Product Instruction
    • 19.4Vector Floating-Point Dot Product Instruction
  • 20Vector Instruction Listing
  • Appendix A: Vector Assembly Code Examples
    • A.1. Vector-vector add example
    • A.2. Example with mixed-width mask and compute.
    • A.3. Memcpy example
    • A.4. Conditional example
    • A.5. SAXPY example
    • A.6. SGEMM example