| Metadata Table | |
|---|---|
| Manual Type | debug |
| Spec Revision | 0.13.2 |
| Spec Release Date | 2019-03-25 |
| Git Revision | task_group_vote-4-g4e0bb0f |
| Git URL | https://github.com/riscv/riscv-debug-spec.git |
| Source | sw_registers.tex |
| Conversion Date | 2023/11/12 |
| License | CC-by-4.0 |
A virtual register is one that doesn’t exist directly in the hardware, but that the debugger exposes as if it does. Debug software should implement them, but hardware can skip this section. Virtual registers exist to give users access to functionality that’s not part of standard debuggers without requiring them to carefully modify debug registers while the debugger is also accessing those same registers.
| Address | Name | Page |
|---|---|---|
| virtual | Privilege Level (priv) |
priv, at virtual)[priv] Users can read this register to inspect the privilege level that the hart was running in when the hart halted. Users can write this register to change the privilege level that the hart will run in when it resumes.
This register contains prvfrom dcsr, but in a place that the user
is expected to access. The user should not access dcsrdirectly,
because doing so might interfere with the debugger.
| Encoding | Privilege Level |
|---|---|
| 0 | User/Application |
| 1 | Supervisor |
| 3 | Machine |
| Field | Description | Access | Reset |
|---|---|---|---|
| [prv] |prv| | Contains the privilege level the hart was operating in when Debug Mode was entered. The encoding is described in Table [tab:privlevel], and matches the privilege level encoding from the Privileged Spec. A user can write this value to change the hart’s privilege level when exiting Debug Mode. | R/W | 0 |